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[bug#60429,v2,1/5] gnu: yosys: Update source and home-page URLs.

Message ID b6c836918f1fd6fb965ea08f44223e5c623948d3.1673202235.git.simon@simonsouth.net
State New
Headers show
Series gnu: yosys: Update to 0.24. | expand

Commit Message

Simon South Jan. 8, 2023, 6:31 p.m. UTC 
* gnu/packages/fpga.scm (yosys)[source]: Update source-repository URL.
[home-page]: Update URL.
---
 gnu/packages/fpga.scm | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index acce5f8f82..45aadf8ea4 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -141,7 +141,7 @@  (define-public yosys
     (source (origin
               (method git-fetch)
               (uri (git-reference
-                    (url "https://github.com/cliffordwolf/yosys")
+                    (url "https://github.com/YosysHQ/yosys")
                     (commit (string-append "yosys-" version))
                     (recursive? #t))) ; for the ‘iverilog’ submodule
               (sha256
@@ -223,7 +223,7 @@  (define-public yosys
            abc))
     (propagated-inputs
      (list z3)) ; should be in path for yosys-smtbmc
-    (home-page "http://www.clifford.at/yosys/")
+    (home-page "https://yosyshq.net/yosys/")
     (synopsis "FPGA Verilog RTL synthesizer")
     (description "Yosys synthesizes Verilog-2005.")
     (license license:isc)))