diff mbox series

[bug#60429,v3,4/5] gnu: yosys: Do not propagate any inputs.

Message ID 2341e855934118580304aaf92195878fc6c71dff.1676033083.git.simon@simonsouth.net
State New
Headers show
Series gnu: yosys: Update to 0.24. | expand

Commit Message

Simon South Feb. 10, 2023, 1:16 p.m. UTC 
* gnu/packages/fpga.scm (yosys)[arguments]<#:phases>: Patch reference to z3 in
"fix-paths" phase; in "use-external-abc" phase, use complete path to "abc"
executable in store.
[propagated-inputs]: Remove, moving abc and z3 from here...
[inputs]: ...to here.
---
 gnu/packages/fpga.scm | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 7b3c522bf7..4a01714e81 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -159,6 +159,9 @@  (define-public yosys
       #~(modify-phases %standard-phases
           (add-before 'configure 'fix-paths
             (lambda* (#:key inputs #:allow-other-keys)
+              (substitute* "./backends/smt2/smtio.py"
+                (("\\['z3")
+                 (string-append "['" (search-input-file inputs "/bin/z3"))))
               (substitute* "./passes/cmds/show.cc"
                 (("exec xdot")
                  (string-append "exec " (search-input-file inputs
@@ -171,9 +174,11 @@  (define-public yosys
             (lambda* (#:key make-flags #:allow-other-keys)
               (apply invoke "make" "config-gcc" make-flags)))
           (add-after 'configure 'use-external-abc
-            (lambda _
+            (lambda* (#:key inputs #:allow-other-keys)
               (substitute* '("./Makefile")
-                (("ABCEXTERNAL \\?=") "ABCEXTERNAL = abc"))))
+                (("ABCEXTERNAL \\?=")
+                 (string-append "ABCEXTERNAL = "
+                                (search-input-file inputs "/bin/abc"))))))
           (add-before 'check 'fix-iverilog-references
             (lambda* (#:key inputs native-inputs #:allow-other-keys)
               (let ((iverilog (search-input-file (or native-inputs inputs)
@@ -211,15 +216,14 @@  (define-public yosys
            python
            tcl)) ; tclsh for the tests
     (inputs
-     (list graphviz
+     (list abc
+           graphviz
            libffi
            psmisc
            readline
            tcl
-           xdot))
-    (propagated-inputs
-     (list abc
-           z3)) ; should be in path for yosys-smtbmc
+           xdot
+           z3))
     (home-page "https://yosyshq.net/yosys/")
     (synopsis "FPGA Verilog RTL synthesizer")
     (description "Yosys synthesizes Verilog-2005.")