@@ -157,16 +157,6 @@ (define-public yosys
(string-append "PREFIX=" #$output))
#:phases
#~(modify-phases %standard-phases
- (add-before 'configure 'fix-paths
- (lambda* (#:key inputs #:allow-other-keys)
- (substitute* "./passes/cmds/show.cc"
- (("exec xdot")
- (string-append "exec " (search-input-file inputs
- "/bin/xdot")))
- (("dot -")
- (string-append (search-input-file inputs "/bin/dot") " -"))
- (("fuser")
- (search-input-file inputs "/bin/fuser")))))
(replace 'configure
(lambda* (#:key make-flags #:allow-other-keys)
(apply invoke "make" "config-gcc" make-flags)))
@@ -211,14 +201,14 @@ (define-public yosys
python
tcl)) ; tclsh for the tests
(inputs
- (list graphviz
- libffi
- psmisc
+ (list libffi
readline
- tcl
- xdot))
+ tcl))
(propagated-inputs
(list abc
+ graphviz ; for dot
+ psmisc ; for fuser
+ xdot
z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")