diff mbox series

[bug#62309,core-updates,v2,1/2] opensbi: Build with default gcc, with microarch rv64g

Message ID f1b2b70c8fca32f850c453775d2e5ad7de5c8ebf.1679389017.git.dev@jpoiret.xyz
State New
Headers show
Series Fix qemu build | expand

Commit Message

Josselin Poiret March 21, 2023, 8:59 a.m. UTC 
* gnu/packages/firmware.scm (make-opensbi-package): Remove specific #:xgcc for
the cross-toolchain, there is not reason for it now.  Also set the microarch to
rv64g, so that it builds.
---
 gnu/packages/firmware.scm | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Maxim Cournoyer March 21, 2023, 4:07 p.m. UTC | #1 
Hello!

Josselin Poiret <dev@jpoiret.xyz> writes:

> * gnu/packages/firmware.scm (make-opensbi-package): Remove specific #:xgcc for
> the cross-toolchain, there is not reason for it now.  Also set the microarch to
> rv64g, so that it builds.
> ---
>  gnu/packages/firmware.scm | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/gnu/packages/firmware.scm b/gnu/packages/firmware.scm
> index 956ece5d6d..0b7fff035a 100644
> --- a/gnu/packages/firmware.scm
> +++ b/gnu/packages/firmware.scm
> @@ -486,7 +486,7 @@ (define* (make-opensbi-package platform name #:optional (arch "riscv64"))
>      (native-inputs
>       `(,@(if (and (not (string-prefix? "riscv64" (%current-system)))
>                    (string-prefix? "riscv64" arch))
> -           `(("cross-gcc" ,(cross-gcc "riscv64-linux-gnu" #:xgcc gcc-7))
> +           `(("cross-gcc" ,(cross-gcc "riscv64-linux-gnu"))
>               ("cross-binutils" ,(cross-binutils "riscv64-linux-gnu")))
>             '())))
>      (arguments
> @@ -499,6 +499,11 @@ (define* (make-opensbi-package platform name #:optional (arch "riscv64"))
>                                  `("CC=gcc"))
>                            "FW_PAYLOAD=n"
>                            "V=1")
> +       ;; Direct __asm__ is used with fence.i instructions, which are not
> +       ;; available in the generic riscv ISA.  We need a micro-arch with
> +       ;; support for it, and rv64g is the official ISA with support for
> +       ;; fence.i.
> +       #:configure-flags (list "-march=rv64g")
>         #:phases
>         (modify-phases %standard-phases
>           (delete 'configure)

LGTM, thanks for expounding the comment as suggested!
diff mbox series

Patch

diff --git a/gnu/packages/firmware.scm b/gnu/packages/firmware.scm
index 956ece5d6d..0b7fff035a 100644
--- a/gnu/packages/firmware.scm
+++ b/gnu/packages/firmware.scm
@@ -486,7 +486,7 @@  (define* (make-opensbi-package platform name #:optional (arch "riscv64"))
     (native-inputs
      `(,@(if (and (not (string-prefix? "riscv64" (%current-system)))
                   (string-prefix? "riscv64" arch))
-           `(("cross-gcc" ,(cross-gcc "riscv64-linux-gnu" #:xgcc gcc-7))
+           `(("cross-gcc" ,(cross-gcc "riscv64-linux-gnu"))
              ("cross-binutils" ,(cross-binutils "riscv64-linux-gnu")))
            '())))
     (arguments
@@ -499,6 +499,11 @@  (define* (make-opensbi-package platform name #:optional (arch "riscv64"))
                                 `("CC=gcc"))
                           "FW_PAYLOAD=n"
                           "V=1")
+       ;; Direct __asm__ is used with fence.i instructions, which are not
+       ;; available in the generic riscv ISA.  We need a micro-arch with
+       ;; support for it, and rv64g is the official ISA with support for
+       ;; fence.i.
+       #:configure-flags (list "-march=rv64g")
        #:phases
        (modify-phases %standard-phases
          (delete 'configure)