@@ -40,6 +40,7 @@ (define-module (gnu packages fpga)
#:use-module (gnu packages base)
#:use-module (gnu packages bison)
#:use-module (gnu packages boost)
+ #:use-module (gnu packages shells)
#:use-module (gnu packages check)
#:use-module (gnu packages cmake)
#:use-module (gnu packages compression)
@@ -106,23 +107,39 @@ (define-public abc
(define-public iverilog
(package
(name "iverilog")
- (version "11.0")
- (source (origin
- (method url-fetch)
- (uri
- (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v11/"
- "verilog-" version ".tar.gz"))
- (sha256
- (base32
- "1mamlrkpb2gb00g7xdddaknrvwi4jr4ng6cfjhwngzk3ddhqaiym"))))
+ (version "12.0")
+ (source
+ (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/steveicarus/iverilog")
+ (commit "v12_0")))
+ (file-name (git-file-name name version))
+ (sha256
+ (base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17"))))
(build-system gnu-build-system)
(arguments
- `(#:make-flags (list (string-append "CC=" ,(cc-for-target)))))
- (native-inputs
- (list flex bison ghostscript zlib)) ; ps2pdf
- (home-page "http://iverilog.icarus.com/")
+ (list
+ #:test-target "check"
+ #:make-flags #~(list (string-append "PREFIX="
+ #$output))
+ #:phases #~(modify-phases %standard-phases
+ (delete 'bootstrap)
+ (add-before 'configure 'autoconf
+ (lambda _
+ (invoke "chmod" "+x" "autoconf.sh")
+ (invoke "./autoconf.sh"))))))
+ (native-inputs (list autoconf bison flex))
+ (inputs (list gawk
+ gperf
+ grep
+ perl
+ sed
+ tcsh))
+ (home-page "https://steveicarus.github.io/iverilog")
(synopsis "FPGA Verilog simulation and synthesis tool")
- (description "Icarus Verilog is a Verilog simulation and synthesis tool.
+ (description
+ "Icarus Verilog is a Verilog simulation and synthesis tool.
It operates as a compiler, compiling source code written in Verilog
(IEEE-1364) into some target format.
For batch simulation, the compiler can generate an intermediate form