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[bug#73918,v3,1/2] gnu: iverilog: Fix yosys tests.

Message ID 69b9ec88a7702cad71742e45d3e8070da903d726.1731179305.git.csantosb@inventati.org
State New
Headers show
Series Minor corrections to v2 | expand

Commit Message

Cayetano Santos Nov. 9, 2024, 7:08 p.m. UTC 
Change-Id: I262db5db43527a3a2a1753163f7b9a4104f7e895

Fixes issue introduced in

  https://git.savannah.gnu.org/cgit/guix.git/commit/?id=b32f8bc9da

which removes zlib. This produces errors when building yosys.

Change-Id: I5b817d176430a0e717597482883d7e806c4552ab
---

See explanation in commit message.

 gnu/packages/fpga.scm | 1 +
 1 file changed, 1 insertion(+)

2.46.0
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Patch

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index c812ed3b7e..ea08aed04c 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -125,7 +125,7 @@  (define-public iverilog
       #:make-flags #~(list (string-append "PREFIX="
                                           #$output))
       #:bootstrap-scripts #~(list "autoconf.sh")))
+    (inputs (list zlib))
     (native-inputs (list autoconf bison flex gperf))
     (home-page "https://steveicarus.github.io/iverilog")
     (synopsis "FPGA Verilog simulation and synthesis tool")
--