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[bug#57291] New package: fftgen

Message ID 20220818231841.vncyowy57s2awb74@silvi
State Accepted
Headers show
Series [bug#57291] New package: fftgen | expand

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Commit Message

Gabriel Wicki Aug. 18, 2022, 11:18 p.m. UTC 
Hi!

I've stumbled upon this beautiful little piece of software that let's
you generate FFT designs in Verilog.  Since it's free software I thought
I'd ready it up for my favorite distribution!

Thanks for merging!

gabriel


From 189ae40cb6104ac703f0171e32fe88208f9fcc25 Mon Sep 17 00:00:00 2001
From: Gabriel Wicki <gabriel@erlikon.ch>
Date: Fri, 19 Aug 2022 01:14:06 +0200
Subject: [PATCH] gnu: Add fftgen.

* gnu/packages/fpga.scm (fftgen): New variable.
---
 gnu/packages/fpga.scm | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

Comments

M Sept. 2, 2022, 6:57 p.m. UTC | #1 
On 19-08-2022 01:18, Gabriel Wicki wrote:
> +                (file-name (git-file-name name
> +                                          (string-take commit 8)))

You don't have to string-take, the standard pattern is (git-file-name 
name version), as in (guix)Version Numbers.

> +       `(#:tests? #f
Why are tests disabled?  There is a bench-test target, maybe you need 
#:test-target "bench-test"? I hope that means "test bench" and not 
"benchmark" though.

On the license: some parts are GPL3+ (see: 
https://github.com/ZipCPU/dblclockfft/blob/master/sw/legal.h), that 
sounds important to add to the license field to me (license 
(license:lgpl3+ license:gpl3+)).

Greetings,
Maxime.
diff mbox series

Patch

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 06d4a10e7e..e1ae577c65 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -552,3 +552,34 @@  (define-public verilator
 performs the design simulation.  Verilator also supports linking its generated
 libraries, optionally encrypted, into other simulators.")
     (license license:lgpl3)))
+
+(define-public fftgen
+  (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08")
+        (revision "0"))
+    (package
+      (name "fftgen")
+      (version (git-version "0" revision commit))
+      (source (origin
+                (method git-fetch)
+                (uri (git-reference
+                      (url "https://github.com/ZipCPU/dblclockfft")
+                      (commit commit)))
+                (file-name (git-file-name name
+                                          (string-take commit 8)))
+                (sha256
+                 (base32
+                  "0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd"))))
+      (build-system gnu-build-system)
+      (arguments
+       `(#:tests? #f
+         #:phases (modify-phases %standard-phases
+                    (delete 'configure)
+                    (replace 'install
+                      (lambda* (#:key outputs #:allow-other-keys)
+                        (let ((bin (string-append (assoc-ref outputs "out")
+                                                  "/bin")))
+                          (install-file "sw/fftgen" bin) #t))))))
+      (synopsis "Generic Pipelined FFT Core Generator")
+      (description "fftgen produces FFT hardware designs in Verilog.")
+      (home-page "https://zipcpu.com/")
+      (license license:lgpl3))))