| Message ID | 20210124174547.27907-1-andrew@interpretmath.pw |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [bug#46069] gnu: Add Verilator. | expand |
| Context | Check | Description |
|---|---|---|
| cbaines/applying patch | fail | View Laminar job |
| cbaines/issue | success | View issue |
Hello, Andrew Miloradovsky <andrew@interpretmath.pw> writes: > * gnu/packages/fpga.scm (verilator): New variable. I added a copyright line for you in "fpga.scm" and applied your patch with the changes detailed below. > + (source (origin > + (method url-fetch) > + (uri (string-append > + "https://github.com/" name "/" > + name "/archive/v" version ".tar.gz")) This is an unstable release, so I used git-fetch instead, with the tag corresponding to the release. > + (native-inputs `(("autoconf" ,autoconf) > + ("automake" ,automake) > + ("gettext" ,gettext-minimal) > + ("perl" ,perl) > + ("python" ,python) > + ("flex" ,flex) > + ("bison" ,bison) > + ("systemc" ,systemc))) I re-ordered native-inputs alphabetically, and moved perl and systemc to regular inputs instead. I'm not absolutely sure about this change, but it still compiles. Let me know if this is not appropriate. > + (synopsis "A fast Verilog/SystemVerilog simulator") I tweaked the synopsis so it doesn't start with the "A" article. Running "guix lint" should warn you about it. > + (description "It compiles SystemVerilog to C++ or SystemC. > +The user writes a little C++/SystemC wrapper file, which instantiates the > +'Verilated' model of the user’s top level module. These C++/SystemC files are > +then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable > +performs the design simulation. Verilator also supports linking its generated > +libraries, optionally encrypted, into other simulators.") I slightly reworded the beginning of the description according to information from the GitHub repository. Thank you. Regards,
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index ff03b5270d..429e848c31 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -496,3 +496,50 @@ components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.") ;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf (license license:asl2.0))) + +(define-public verilator + (package + (name "verilator") + (version "4.108") + (source (origin + (method url-fetch) + (uri (string-append + "https://github.com/" name "/" + name "/archive/v" version ".tar.gz")) + (file-name (string-append name "-" version ".tar.gz")) + (sha256 + (base32 + "0mbwplrkmp06clm1y3p33n74qrr3rqsc803hzwjs7ralfz2islnf")))) + (native-inputs `(("autoconf" ,autoconf) + ("automake" ,automake) + ("gettext" ,gettext-minimal) + ("perl" ,perl) + ("python" ,python) + ("flex" ,flex) + ("bison" ,bison) + ("systemc" ,systemc))) + (build-system gnu-build-system) + (arguments '(#:configure-flags + (list (string-append "LDFLAGS=-L" + (assoc-ref %build-inputs "systemc") + "/lib-linux64")) + #:make-flags + (list (string-append "LDFLAGS=-L" + (assoc-ref %build-inputs "systemc") + "/lib-linux64")) + #:phases + (modify-phases %standard-phases + (replace 'bootstrap + (lambda _ (invoke "autoconf")))) + #:test-target "test")) + ;; #error "Something failed during ./configure as config_build.h is incomplete. + ;; Perhaps you used autoreconf, don't." -- so we won't. ^ + (home-page "https://www.veripool.org/projects/verilator/") + (synopsis "A fast Verilog/SystemVerilog simulator") + (description "It compiles SystemVerilog to C++ or SystemC. +The user writes a little C++/SystemC wrapper file, which instantiates the +'Verilated' model of the user’s top level module. These C++/SystemC files are +then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable +performs the design simulation. Verilator also supports linking its generated +libraries, optionally encrypted, into other simulators.") + (license license:lgpl3)))